TY - GEN
T1 - An Analog-assisted Fast-transient Digital LDO with a Charge-pump-based Fine Loop Achieving 0.14-mV Output Voltage Ripples
AU - Qaisar, Shirin
AU - Akram, Muhammad Abrar
AU - Haris Farooq, Muhammad
AU - Kweon, Soon Jae
AU - Cheema, Hammad M.
AU - Ha, Sohmyung
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) of < 140 μV and a minimum dropout voltage of 20 mV, for driving both noise-sensitive analog and power-efficient digital load circuits in system-on-chip devices. To eliminate VRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm2. The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOAD of 75 mA with a peak current efficiency of 99.93 %.
AB - This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) of < 140 μV and a minimum dropout voltage of 20 mV, for driving both noise-sensitive analog and power-efficient digital load circuits in system-on-chip devices. To eliminate VRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm2. The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOAD of 75 mA with a peak current efficiency of 99.93 %.
KW - analog-assistance
KW - Digital low-dropout regulator
KW - fast-transient
KW - power efficiency
KW - ripple-less
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U2 - 10.1109/ISCAS58744.2024.10557926
DO - 10.1109/ISCAS58744.2024.10557926
M3 - Conference contribution
AN - SCOPUS:85198525866
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2024 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Y2 - 19 May 2024 through 22 May 2024
ER -