An approach to energy-error tradeoffs in approximate ripple carry adders

Zvi M. Kedem, Vincent J. Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90nm transistor technology.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages211-216
Number of pages6
DOIs
StatePublished - 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: Aug 1 2011Aug 3 2011

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CountryJapan
CityFukuoka
Period8/1/118/3/11

Keywords

  • Approximate Adders
  • Geometric Programming
  • Low Energy Circuits
  • Voltage Scaling

ASJC Scopus subject areas

  • Engineering(all)

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