As a new generation of power MOSFETs, COOLMOS has recently found an especial scope in power electronics. After the conceptual development of the relative voltage sustaining structure [1-3], COOLMOS has been experimentally realized to break the limit line of silicon in high voltage applications . The main building block of these devices is a combination of parallel NAND p strips called a superjunction, as shown in Fig.1(a), whereas the conventional voltagesustaining block is a low-doped drift region given in Fig.l(b). It is the unique capability of the super-junction that guarantees efficient voltage sustaining, when the transistor is in the OFF-state. Properties of the swcalled superjunction as well as modeling and optimization of the complete device structure has been pursued in previous works [5,6]. In this contribution, we are concemed with the fabrication process. As may be concluded from Fig.1(a), formation of columnar n- and p strips is an expensive process, since these regions should be formed by multiple deposition of epitaxial layers and subsequent implantation steps. For instance, the use of masked boron and phosphor implantations on undoped epitaxy on a highly doped n' substrate has been reported . A diffusion process is subsequently employed to form vertically coherent n- and p columns. It is apparent that with columns as large as 20 pm, more than IO steps of epitaxy and implantation might be needed, which directly translates into the high cost of the fabrication process. We hereby propose a lateral fabrication method during which only one epitaxy step is involved. The only extra cost would be due to the initial SO1 substrates, which is negligible in comparison with the cost reduction, resulted by eliminating the frequent epitaxy steps. Our proposed structure is schematically given in Fig.2(a), where the conventional vertical structure is also given for comparison in Fig.2(b). We have simulated the fabrication process of the proposed structure with DIOS simulator in GENESISe . An ntype SO1 wafer with a thickness of 2.5 μm concentration of 10l6 cm-' is chosen as the initial substrate. The n upper layer of the SO1 wafer serves as the n drift pillar. The 2 .5 μm pst rip is formed by epitaxial growth and with the same doping in boron ambient. The pwell is formed by oxide-masked multiple implantations of boron with maximum energy of 250KeV and surface dose of 10'3cm-2, followed by a 300-minute annealing for drive-in. The needed space for the drain contact is grooved by RIE and filled with CVD-deposited highly doped PSG via standard lithography and CMP steps. The gate space is also grooved by RIE and a 180-minutes thermal oxidation period at 1100°C forms the 250nmthick gate oxide. During this annealing period, the n' drain contact is also formed by diffision of phosphorous from PSG into the Si region. The n' source region is formed by resist-masked implantation of antimony, followed by annealing to activate the dopants. After removing the PSG previously deposited into the drain trench by RIE, tungsten is deposited to f m th e gate and the drain contacts. After patteming the metal layer and CMF', tungsten is again deposited and patterned to form the source contact. Adjacent devices may be isolated by removing the dashed regions shown in the figure, via an arbitrary etching process, such as NE. Dessis simulator has been employed to characterize the COOLMOS structure simulated by DIOS and the b-vm and ID-VGs curves are given in Fig.3 and Fig.4, respectively. These curves exhibit a similar behavior as the conventional vertical structure . The depletion region edge during ON-state operation of the proposed structure is depicted in Fig.5, for various values of the drain-source voltage. This plot shows the onset of quasi-saturation at gate-source voltages around 1OV and corroborates the ID-VDcs urves of Fig. 4. The simulated values of the electric field across the line y=3.5μm is also given in Fig. 6 for different drain-source voltages. The Dessis simulations confirm the functionality of the proposed device structure. Considering the fact that all of the steps in OUT process flow are compatible with standard CMOS technology, this method puts forth the chance of on-chip realization for the lateral C0"OLMOS structures. Eliminating the frequent epitaxy steps is the other advantage of this proposal, which reduces the total cost of the fabrication process considerably.