TY - GEN
T1 - An artificial neural network-based hotspot prediction mechanism for NoCs
AU - Kakoullit, Elena
AU - Soteriou, Vassos
AU - Theocharides, Theocharis
PY - 2010
Y1 - 2010
N2 - Hotspots are network on-chip (NoC) routers or modules in systems on-chip (SoCs) which occasionally receive packetized traffic at a rate higher than they can consume It. This adverse phenomenon greatly reduces the performance of an NoC, especially in the case of today's widely-employed wormhole flow-control, as backpressure can cause the buffers of neighboring routers to quickly fill-up leading to a spatial spread in congestion that can cause the network to saturate. Even worse, such situations may lead to deadlocks. Thus, a hotspot prevention mechanism can be greatly beneficial, as it can potentially enable the interconnection system to adjust its behavior and prevent the rise of potential hotspots, subsequently sustaining NoC performance and efficiency. Unfortunately, hotspots cannot be known a-priori In NoCs used in general-purpose systems as application demands are not predetermined unlike in application-specific SoCs, making hotspot prediction and subsequently prevention difficult. In this paper we present an artificial neural network-based hotspot prediction mechanism that can be potentially used in tandem with a hotspot avoidance mechanism for handling an unforeseen hotspot formation efficiently. The network uses buffer utilization statistical data to dynamically monitor the interconnect fabric, and reactively predicts the location of an about to-be-formed hotspot, allowing enough time for the system to react to these potential hotspots. The neural network is trained using synthetic traffic models, and evaluated using both synthetic and real application traces. Results indicate that a relatively small neural network can predict hotspot formation with accuracy ranges between 76% to 92% when evaluated on two different mesh NoCs.
AB - Hotspots are network on-chip (NoC) routers or modules in systems on-chip (SoCs) which occasionally receive packetized traffic at a rate higher than they can consume It. This adverse phenomenon greatly reduces the performance of an NoC, especially in the case of today's widely-employed wormhole flow-control, as backpressure can cause the buffers of neighboring routers to quickly fill-up leading to a spatial spread in congestion that can cause the network to saturate. Even worse, such situations may lead to deadlocks. Thus, a hotspot prevention mechanism can be greatly beneficial, as it can potentially enable the interconnection system to adjust its behavior and prevent the rise of potential hotspots, subsequently sustaining NoC performance and efficiency. Unfortunately, hotspots cannot be known a-priori In NoCs used in general-purpose systems as application demands are not predetermined unlike in application-specific SoCs, making hotspot prediction and subsequently prevention difficult. In this paper we present an artificial neural network-based hotspot prediction mechanism that can be potentially used in tandem with a hotspot avoidance mechanism for handling an unforeseen hotspot formation efficiently. The network uses buffer utilization statistical data to dynamically monitor the interconnect fabric, and reactively predicts the location of an about to-be-formed hotspot, allowing enough time for the system to react to these potential hotspots. The neural network is trained using synthetic traffic models, and evaluated using both synthetic and real application traces. Results indicate that a relatively small neural network can predict hotspot formation with accuracy ranges between 76% to 92% when evaluated on two different mesh NoCs.
UR - http://www.scopus.com/inward/record.url?scp=77957902517&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77957902517&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2010.50
DO - 10.1109/ISVLSI.2010.50
M3 - Conference contribution
AN - SCOPUS:77957902517
SN - 9780769540764
T3 - Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
SP - 339
EP - 344
BT - Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
T2 - IEEE Annual Symposium on VLSI, ISVLSI 2010
Y2 - 5 July 2010 through 7 July 2010
ER -