The asynchronous transfer mode (ATM) technique provides a flexible and effective scheme to transport traffic generated by a variety of services with different quality of service (QOS) requirements. To fully utilize network resources while still providing satisfactory QOS to all network users, prioritizing different traffic according to their service requirement becomes necessary. During the call setup, each service can be assigned a service class determined by a delay priority and a loss priority. A queue manager in ATM network nodes will schedule ATM cells' departing and discarding sequence based on their delay and loss priorities. Most queue management schemes that have been proposed only consider either one of these two priority types. In this paper, the queue manager treats multiple delay and loss priority simultaneously. Moreover, a cell discarding strategy, called push out with a buffer completely shared by all service classes, has been adopted in the queue manager. We propose a feasible architecture to implement the queue manager by using available VLSI Sequencer chips.