TY - GEN
T1 - An optimized application architecture of the H.264 video encoder for application specific platforms
AU - Shafique, Muhammad
AU - Bauer, Lars
AU - Henkel, Jörg
N1 - Copyright:
Copyright 2009 Elsevier B.V., All rights reserved.
PY - 2007
Y1 - 2007
N2 - The H.264 video coding standard features diverse computational hot spots that need to be accelerated to cope with the significantly increased complexity compared to previous standards. In this paper, we propose an optimized application architecture for the H.264 encoder with reduced processing and which is suitable for application specific (reconfigurable) hardware platforms. Our proposed application architecture optimization for the computational amount of the Motion Compensation (MC) is independent of the actual hardware platform that is used for execution. For a MIPS processor we achieve an average speed-up of approx. 60x for MC. Our proposed application architecture reduces the overhead for Reconfigurable Platforms by distributing the actual hardware requirements amongst the functional blocks. This increases the amount of available reconfigurable hardware per data path (within a functional block) which leads to a 2.84x performance improvement. We evaluate our application architecture by means of four different hardware platforms.
AB - The H.264 video coding standard features diverse computational hot spots that need to be accelerated to cope with the significantly increased complexity compared to previous standards. In this paper, we propose an optimized application architecture for the H.264 encoder with reduced processing and which is suitable for application specific (reconfigurable) hardware platforms. Our proposed application architecture optimization for the computational amount of the Motion Compensation (MC) is independent of the actual hardware platform that is used for execution. For a MIPS processor we achieve an average speed-up of approx. 60x for MC. Our proposed application architecture reduces the overhead for Reconfigurable Platforms by distributing the actual hardware requirements amongst the functional blocks. This increases the amount of available reconfigurable hardware per data path (within a functional block) which leads to a 2.84x performance improvement. We evaluate our application architecture by means of four different hardware platforms.
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U2 - 10.1109/ESTMED.2007.4375816
DO - 10.1109/ESTMED.2007.4375816
M3 - Conference contribution
AN - SCOPUS:47849130862
SN - 9781424416547
T3 - Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007
SP - 119
EP - 124
BT - Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007
T2 - 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007
Y2 - 4 October 2007 through 5 October 2007
ER -