TY - JOUR
T1 - An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO
AU - Choi, Injun
AU - Choi, Edward Jongyoon
AU - Yi, Donghyeon
AU - Jung, Yoontae
AU - Seong, Hoyong
AU - Jeon, Hyuntak
AU - Kweon, Soon Jae
AU - Chang, Ik Joon
AU - Ha, Sohmyung
AU - Je, Minkyu
N1 - Publisher Copyright:
© 2011 IEEE.
PY - 2022/6/1
Y1 - 2022/6/1
N2 - This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential current-controlled-oscillator (DCCO). After the phase-domain accumulation is completed, only a one-time digital conversion needs to be performed using a phase quantizer with negligible phase-to-digital conversion overhead. Moreover, by effectively reusing the steered current to accumulate the multiplication results fed from the DIMAC, the power consumption of the PNMAC can be greatly reduced. The macro fabricated in a 65 nm process achieves 22.4TOPS/W peak energy efficiency and 19.03~mu text{W} power consumption with a 59.8% zero-skipping rate, which is 96.05times lower than state of the art.
AB - This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential current-controlled-oscillator (DCCO). After the phase-domain accumulation is completed, only a one-time digital conversion needs to be performed using a phase quantizer with negligible phase-to-digital conversion overhead. Moreover, by effectively reusing the steered current to accumulate the multiplication results fed from the DIMAC, the power consumption of the PNMAC can be greatly reduced. The macro fabricated in a 65 nm process achieves 22.4TOPS/W peak energy efficiency and 19.03~mu text{W} power consumption with a 59.8% zero-skipping rate, which is 96.05times lower than state of the art.
KW - computation in memory (CIM)
KW - Convolutional neural network (CNN)
KW - differential current-controlled-oscillator (DCCO)
KW - digital in-memory-array computing (DIMAC)
KW - phase-domain near-memory-array computing (PNMAC)
KW - SRAM
UR - http://www.scopus.com/inward/record.url?scp=85129422068&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85129422068&partnerID=8YFLogxK
U2 - 10.1109/JETCAS.2022.3170595
DO - 10.1109/JETCAS.2022.3170595
M3 - Article
AN - SCOPUS:85129422068
SN - 2156-3357
VL - 12
SP - 536
EP - 546
JO - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
JF - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
IS - 2
ER -