An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO

Injun Choi, Edward Jongyoon Choi, Donghyeon Yi, Yoontae Jung, Hoyong Seong, Hyuntak Jeon, Soon Jae Kweon, Ik Joon Chang, Sohmyung Ha, Minkyu Je

Research output: Contribution to journalArticlepeer-review


This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential current-controlled-oscillator (DCCO). After the phase-domain accumulation is completed, only a one-time digital conversion needs to be performed using a phase quantizer with negligible phase-to-digital conversion overhead. Moreover, by effectively reusing the steered current to accumulate the multiplication results fed from the DIMAC, the power consumption of the PNMAC can be greatly reduced. The macro fabricated in a 65 nm process achieves 22.4TOPS/W peak energy efficiency and 19.03~mu text{W} power consumption with a 59.8% zero-skipping rate, which is 96.05times lower than state of the art.

Original languageEnglish (US)
Pages (from-to)536-546
Number of pages11
JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Issue number2
StatePublished - Jun 1 2022


  • computation in memory (CIM)
  • Convolutional neural network (CNN)
  • differential current-controlled-oscillator (DCCO)
  • digital in-memory-array computing (DIMAC)
  • phase-domain near-memory-array computing (PNMAC)
  • SRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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