TY - JOUR
T1 - An Ultra-low-power Amplifier-less Potentiostat Design Based on Digital Regulation Loop
AU - Akram, Muhammad Abrar
AU - Aberra, Aida
AU - Kweon, Soon Jae
AU - Ha, Sohmyung
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - This paper presents a new potentiostat circuit architecture for interfaces with amperometric electrochemical biosensors. The proposed architecture, which is based on a digital low-dropout regulator (DLDO) structure, successfully eliminates the need for transimpedance amplifier (TIA), control amplifier, and other passive elements unlike other typical potentiostat topologies. It can regulate the required electrode voltages and measure the sensor currents (ISENSE) at the same time by using a simple implementation with clocked comparators, digital loop filters, and current-steering DACs. Three different configurations of the proposed potentiostat are discussed including single-side regulated (SSR) potentiostat, dual-side regulated (DSR) potentiostat, and differential sensing DSR potentiostat with a background working electrode. These proposed potentiostats were designed and fabricated in a 180 nm CMOS process, occupying an active silicon areas of 0.0645 mm2, 0.1653 mm2, and 0.266 mm2, respectively. Validation results demonstrate that the proposed potentiostats operate on a wide sampling frequency range from 100 Hz to 100 MHz and supply voltage range from 1 V to 1.8 V. The proposed DSR potentiostat achieves a minimal power consumption of 3.7 nW over the entire dynamic range of 129.5 dB.
AB - This paper presents a new potentiostat circuit architecture for interfaces with amperometric electrochemical biosensors. The proposed architecture, which is based on a digital low-dropout regulator (DLDO) structure, successfully eliminates the need for transimpedance amplifier (TIA), control amplifier, and other passive elements unlike other typical potentiostat topologies. It can regulate the required electrode voltages and measure the sensor currents (ISENSE) at the same time by using a simple implementation with clocked comparators, digital loop filters, and current-steering DACs. Three different configurations of the proposed potentiostat are discussed including single-side regulated (SSR) potentiostat, dual-side regulated (DSR) potentiostat, and differential sensing DSR potentiostat with a background working electrode. These proposed potentiostats were designed and fabricated in a 180 nm CMOS process, occupying an active silicon areas of 0.0645 mm2, 0.1653 mm2, and 0.266 mm2, respectively. Validation results demonstrate that the proposed potentiostats operate on a wide sampling frequency range from 100 Hz to 100 MHz and supply voltage range from 1 V to 1.8 V. The proposed DSR potentiostat achieves a minimal power consumption of 3.7 nW over the entire dynamic range of 129.5 dB.
KW - amperometry
KW - and current readout IC
KW - current sensing
KW - Electrochemical sensing
KW - power efficiency
KW - wide dynamic range
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U2 - 10.1109/TBCAS.2025.3527652
DO - 10.1109/TBCAS.2025.3527652
M3 - Article
AN - SCOPUS:85214786926
SN - 1932-4545
JO - IEEE Transactions on Biomedical Circuits and Systems
JF - IEEE Transactions on Biomedical Circuits and Systems
ER -