An updated survey of efficient hardware architectures for accelerating deep convolutional neural networks

Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Muhammad Shafique, Guido Masera, Maurizio Martina

Research output: Contribution to journalReview articlepeer-review

Abstract

Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand they present cutting edge performance, on the other hand they require enormous computing power. For this reason, numerous optimization techniques at the hardware and software level, and specialized architectures, have been developed to process these models with high performance and power/energy efficiency without affecting their accuracy. In the past, multiple surveys have been reported to provide an overview of different architectures and optimization techniques for efficient execution of Deep Learning (DL) algorithms. This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs. In this paper, the reader will first understand what a hardware accelerator is, and what are its main components, followed by the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

Original languageEnglish (US)
Article number113
JournalFuture Internet
Volume12
Issue number7
DOIs
StatePublished - Jul 2020

Keywords

  • AI
  • Area
  • Artificial intelligence
  • CNNs
  • Computer architecture
  • Convolutional neural networks
  • Data flow
  • Deep learning
  • Deep neural networks
  • DNNs
  • Efficiency
  • Energy
  • Hardware accelerator
  • Latency
  • Machine learning
  • Optimization
  • Performance
  • Power consumption
  • VLSI

ASJC Scopus subject areas

  • Computer Networks and Communications

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