Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms

Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew Kennings

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Thread migration (TM) is a recently proposed dynamic power management technique for heterogeneous multi-processor system-on-chip (MPSoC) platforms that eliminates the area and power overheads incurred by fine-grained dynamic voltage and frequency scaling (DVFS) based power management. In this paper, we take the first step towards formally analyzing and experimentally evaluating the use of power-aware TM for parallel data streaming applications on MPSoC platforms. From an analysis perspective, we characterize the optimal mapping of threads to cores and prove the convergence properties of a complexity effective greedy thread swapping based TM algorithm to the globally optimal solution. The proposed techniques are evaluated on a 9-core FPGA based MPSoC prototype equipped with fully-functional TM and DVFS support, and running a parallelized video encoding benchmark based on the Motion Picture Experts Group (MPEG-2) standard. Our experimental results validate the proposed theoretical analysis, and show that the proposed TM algorithm provides within 8% of the DVFS performance under the same power budget, and assuming no overheads for DVFS. Assuming voltage regulator inefficiency of 80%, the proposed TM algorithm has 9% higher performance than DVFS, again under the same total power budget.

Original languageEnglish (US)
Title of host publicationProceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
Pages617-624
Number of pages8
DOIs
StatePublished - 2012
Event13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States
Duration: Mar 19 2012Mar 21 2012

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other13th International Symposium on Quality Electronic Design, ISQED 2012
CountryUnited States
CitySanta Clara, CA
Period3/19/123/21/12

Keywords

  • DVFS
  • FPGA
  • Multi-core
  • Power management
  • Thread migration

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Ravishankar, C., Ananthanarayanan, S., Garg, S., & Kennings, A. (2012). Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. In Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012 (pp. 617-624). [6187557] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2012.6187557