Application of serial transformations in scan-based SOC test for test cost reduction

Increased core test parallelism translates into reduced System On a Chip (SOC) test application time. Yet, the availability of a limited number of tester channels hampers this parallelism. Furthermore, the test vectors to be delivered into core scan chains need to be stored in the tester memory, imposing considerable costs on SOC tests. In this paper, a pair of SOC test methodologies delivering enhanced core test access, while ensuring fault coverage levels identical to those attained in deterministic test are proposed. In the first proposed methodology, namely the self yet deterministic core test approach, a single Linear Feedback Shift Register (LFSR) broadcasts pseudo-random patterns to each core. The LFSR patterns are transformed into the actual test vectors of a core while they are being shifted into the core scan chain. In the other proposed approach, namely the pipelined core test approach, the response of the preceding core is transmuted into the test vector of the next core during shift cycles. In both approaches, the transformation is realized through the logic gates inserted seamlessly between the core scan cells during shift cycles. The efficacy and the cost-effectiveness of the proposed methodologies reflects into significantly reduced test costs.