ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems

Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasicek; Lukas Sekanina; Muhammad Shafique

doi:10.1109/DAC18072.2020.9218533

ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems

Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasicek, Lukas Sekanina, Muhammad Shafique

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.

Original language	English (US)
Title of host publication	2020 57th ACM/IEEE Design Automation Conference, DAC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450367257
DOIs	https://doi.org/10.1109/DAC18072.2020.9218533
State	Published - Jul 2020
Event	57th ACM/IEEE Design Automation Conference, DAC 2020 - Virtual, San Francisco, United States Duration: Jul 20 2020 → Jul 24 2020

Publication series

Name	Proceedings - Design Automation Conference
Volume	2020-July
ISSN (Print)	0738-100X

Conference

Conference	57th ACM/IEEE Design Automation Conference, DAC 2020
Country/Territory	United States
City	Virtual, San Francisco
Period	7/20/20 → 7/24/20

Keywords

Adder
Approximate Computing
Arithmetic Units
ASIC
FPGA
Machine Learning
Models
Multiplier
Statistics
Synthesis

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Access to Document

10.1109/DAC18072.2020.9218533

Cite this

Prabakaran, B. S., Mrazek, V., Vasicek, Z., Sekanina, L., & Shafique, M. (2020). ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems. In 2020 57th ACM/IEEE Design Automation Conference, DAC 2020 Article 9218533 (Proceedings - Design Automation Conference; Vol. 2020-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DAC18072.2020.9218533

ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems. / Prabakaran, Bharath Srinivas; Mrazek, Vojtech; Vasicek, Zdenek et al.
2020 57th ACM/IEEE Design Automation Conference, DAC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9218533 (Proceedings - Design Automation Conference; Vol. 2020-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Prabakaran, BS, Mrazek, V, Vasicek, Z, Sekanina, L & Shafique, M 2020, ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems. in 2020 57th ACM/IEEE Design Automation Conference, DAC 2020., 9218533, Proceedings - Design Automation Conference, vol. 2020-July, Institute of Electrical and Electronics Engineers Inc., 57th ACM/IEEE Design Automation Conference, DAC 2020, Virtual, San Francisco, United States, 7/20/20. https://doi.org/10.1109/DAC18072.2020.9218533

@inproceedings{2551026112704d6aaf6b67d7977fdb9e,

title = "ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems",

abstract = "There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.",

keywords = "Adder, Approximate Computing, Arithmetic Units, ASIC, FPGA, Machine Learning, Models, Multiplier, Statistics, Synthesis",

author = "Prabakaran, {Bharath Srinivas} and Vojtech Mrazek and Zdenek Vasicek and Lukas Sekanina and Muhammad Shafique",

note = "Funding Information: ACKNOWLEDGEMENT This work was partially supported by Doctoral College Resilient Embedded Systems which is run jointly by TU Wien{\textquoteright}s Faculty of Informatics and FH-Technikum Wien, and partially by Czech Science Foundation project 19-10137S. Publisher Copyright: {\textcopyright} 2020 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 57th ACM/IEEE Design Automation Conference, DAC 2020 ; Conference date: 20-07-2020 Through 24-07-2020",

year = "2020",

month = jul,

doi = "10.1109/DAC18072.2020.9218533",

language = "English (US)",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 57th ACM/IEEE Design Automation Conference, DAC 2020",

}

TY - GEN

T1 - ApproxFPGAs

T2 - 57th ACM/IEEE Design Automation Conference, DAC 2020

AU - Prabakaran, Bharath Srinivas

AU - Mrazek, Vojtech

AU - Vasicek, Zdenek

AU - Sekanina, Lukas

AU - Shafique, Muhammad

N1 - Funding Information: ACKNOWLEDGEMENT This work was partially supported by Doctoral College Resilient Embedded Systems which is run jointly by TU Wien’s Faculty of Informatics and FH-Technikum Wien, and partially by Czech Science Foundation project 19-10137S. Publisher Copyright: © 2020 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.

PY - 2020/7

Y1 - 2020/7

N2 - There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.

AB - There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.

KW - Adder

KW - Approximate Computing

KW - Arithmetic Units

KW - ASIC

KW - FPGA

KW - Machine Learning

KW - Models

KW - Multiplier

KW - Statistics

KW - Synthesis

UR - http://www.scopus.com/inward/record.url?scp=85093978304&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85093978304&partnerID=8YFLogxK

U2 - 10.1109/DAC18072.2020.9218533

DO - 10.1109/DAC18072.2020.9218533

M3 - Conference contribution

AN - SCOPUS:85093978304

T3 - Proceedings - Design Automation Conference

BT - 2020 57th ACM/IEEE Design Automation Conference, DAC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 20 July 2020 through 24 July 2020

ER -

ApproxFPGAs: Embracing ASIC-Based approximate arithmetic components for FPGA-Based systems

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this