Approximation-aware Multi-Level Cells STT-RAM cache architecture

Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Current manycore processors exhibit large on-chip last-level caches that may reach sizes of 32MB - 128MB and incur high power/energy consumption. The emerging Multi-Level Cells (MLC) STT-RAM memory technology improves the capacity and energy efficiency issues of large-sized memory banks. However, MLC STT-RAM incurs non-negligible protection overhead to ensure reliable operations when compared to the Single-Level Cells (SLC) STT-RAM. In this paper, we propose an approximation-aware MLC STT-RAM cache architecture, which is partially-protected to restrict the reliability overhead and in turn leverages variable resilience characteristics of different applications for adaptively curtailing the protection overhead under a given error tolerance level. It thereby improves the energy-efficiency of the cache while meeting the reliability requirements. Our cache architecture is equipped with a latency-aware hardware module for double-error correction. To achieve high energy efficiency, approximation-aware read and write policies are proposed that perform approximate storage management while tolerating some errors bounded within the user-provided tolerance level. The architecture also facilitates runtime control on the quality of applications' results. We perform a case study on the next-generation advanced video encoding that exhibit memory-intensive functional blocks with varying resilience properties and support for parallelism. Experimental results demonstrate that our approximation-aware MLC STT-RAM based cache architecture can improve the energy efficiency compared to state-of-the-art fully-protected caches (7%-19%, on average), while incurring minimal quality penalties in the output (-0.219% to -0.426%, on average). Furthermore, our architecture supports complete error protection coverage for all cache data when processing non-resilient application. The hardware overhead to implement our approximation-aware management negligibly affects the energy efficiency (0.15%-1.3% of overhead) and the access latency (only 0.02%-1.56% of overhead).

Original languageEnglish (US)
Title of host publication2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages79-88
Number of pages10
ISBN (Electronic)9781467383202
DOIs
StatePublished - Nov 10 2015
EventInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015 - Amsterdam, Netherlands
Duration: Oct 4 2015Oct 9 2015

Publication series

Name2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015

Conference

ConferenceInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
CountryNetherlands
CityAmsterdam
Period10/4/1510/9/15

Keywords

  • Approximation methods
  • Magnetic tunneling
  • Memory management
  • Random access memory
  • Reliability
  • Resilience

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Science Applications

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