@inproceedings{010c5741c47448239e197cc0ed553c72,
title = "AR-CIM: A 460.22TOPS/W SRAM-based Analog Reconfigurable Computing-in-Memory Macro with 1/2/4/8-Bit Variable Precision",
abstract = "This work presents an SRAM-based analog reconfigurable computing-in-memory macro with 409.6-GOPS throughput and 460.22-TOPS/W energy efficiency. The proposed reconfigurable macro supports 1/2/4/8b inputs and 1/2/4/8b signed weights while maintaining 100% memory utilization. Furthermore, we propose (i) a dual-domain DAC to achieve high-precision input with low area overhead and (ii) an input-sense-and-skip SAR ADC, which reduces the average power overhead by 54% compared with conventional SAR ADC.",
keywords = "Analog Computing-in-memory (ACIM), Convolution Neural Network, SRAM",
author = "Byeongseon Choi and Edward Choi and Donghyeon Yi and Jiho Chun and Sohmyung Ha and Chang, {Ik Joon} and Minkyu Je",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 ; Conference date: 09-09-2024 Through 12-09-2024",
year = "2024",
doi = "10.1109/ESSERC62670.2024.10719461",
language = "English (US)",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "361--364",
booktitle = "ESSERC 2024 - Proceedings",
}