Abstract
We have proposed a new architecture for building a scalable multicast ATM switch from a few tens to a few thousands of input/output ports. The switch, called the Abacus switch, employs input and output buffering scheme. Cell replication, cell routing, and output contention resolution are all performed in a distributed way so that the switch can be scaled up to a large size. The switch can also handle multiple priority traffic by routing cells according to their priority levels. This paper describes a key ASIC chip for building the Abacus switch. The chip, called the ARC (ATM Routing and Concentration) chip, contains a two-dimensional array (32×32) of switch elements that are arranged in a cross-bar structure. The ARC chip has been designed and fabricated using 0.8-μm CMOS technology and tested to operate correctly at 240 MHz.
| Original language | English (US) |
|---|---|
| Pages | 102-107 |
| Number of pages | 6 |
| State | Published - 1997 |
| Event | Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China Duration: Jun 3 1997 → Jun 5 1997 |
Other
| Other | Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications |
|---|---|
| City | Taipei, China |
| Period | 6/3/97 → 6/5/97 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering