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ARC: An ATM routing and concentration chip
H. Jonathan Chao
, Necdet Uzun
Electrical and Computer Engineering
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peer-review
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Keyphrases
Abacus
100%
Two-dimensional Array
50%
Input-output
50%
Output Port
50%
Contention Resolution
50%
Crossbar
50%
CMOS Technology
50%
Cell Replication
50%
Buffering Mechanisms
50%
Switching Element
50%
New Architecture
50%
Scalable Multicast
50%
Priority Traffic
50%
Multiple Priorities
50%
Priority Level
50%
ASIC chip
50%
Computer Science
Input/Output
100%
Two-Dimensional Array
100%
Contention Resolution
100%
Application Specific Integrated Circuit
100%
Multicasting
100%
Priority Traffic
100%
Engineering
Automatic Teller Machines
100%
Two Dimensional
20%
Dimensional Array
20%
Application Specific Integrated Circuit
20%
Contention
20%
Output Port
20%
Bar Structure
20%
Cross Bar
20%
Priority Level
20%