TY - GEN
T1 - Architectural-space exploration of approximate multipliers
AU - Rehman, Semeen
AU - El-Harouni, Walaa
AU - Shafique, Muhammad
AU - Kumar, Akash
AU - Henkel, Jörg
N1 - Publisher Copyright:
© 2016 ACM.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/11/7
Y1 - 2016/11/7
N2 - This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates various design points by adapting three key parameters: (1) different types of elementary approximate multiply modules, (2) different types of elementary adder modules for summing the partial products, and (3) selection of bits for approximation in a wide-bit multiplier design. Generation and exploration of such a design space enables a wide-range of multipliers with varying approximation levels, each exhibiting distinct area, power, and output quality, and thereby facilitates approximate computing at higher abstraction levels. We synthesized our designs using Synopsys Design Compiler with a TSMC 45nm technology library and verified using ModelSim gatelevel simulations. Power and quality evaluations for various designs are performed using PrimeTime and behavioral models, respectively. The selected designs are then deployed in a JPEG application. For reproducibility and to facilitate further research and development at higher abstraction layers, we have released the RTL and behavioral models of these approximate multipliers and adders as an open-source library at https://sourceforge.net/projects/lpaclib/.
AB - This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates various design points by adapting three key parameters: (1) different types of elementary approximate multiply modules, (2) different types of elementary adder modules for summing the partial products, and (3) selection of bits for approximation in a wide-bit multiplier design. Generation and exploration of such a design space enables a wide-range of multipliers with varying approximation levels, each exhibiting distinct area, power, and output quality, and thereby facilitates approximate computing at higher abstraction levels. We synthesized our designs using Synopsys Design Compiler with a TSMC 45nm technology library and verified using ModelSim gatelevel simulations. Power and quality evaluations for various designs are performed using PrimeTime and behavioral models, respectively. The selected designs are then deployed in a JPEG application. For reproducibility and to facilitate further research and development at higher abstraction layers, we have released the RTL and behavioral models of these approximate multipliers and adders as an open-source library at https://sourceforge.net/projects/lpaclib/.
KW - adder
KW - approximate computing
KW - area
KW - arithmetic
KW - configurable accuracy
KW - design space exploration
KW - library
KW - low power image processing
KW - multiplier
KW - open source
KW - performance
KW - power
UR - http://www.scopus.com/inward/record.url?scp=85001103597&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85001103597&partnerID=8YFLogxK
U2 - 10.1145/2966986.2967005
DO - 10.1145/2966986.2967005
M3 - Conference contribution
AN - SCOPUS:85001103597
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016
Y2 - 7 November 2016 through 10 November 2016
ER -