TY - GEN
T1 - Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators
AU - Ullah, Salim
AU - Rehman, Semeen
AU - Prabakaran, Bharath Srinivas
AU - Kriebel, Florian
AU - Hanif, Muhammad Abdullah
AU - Shafique, Muhammad
AU - Kumar, Akash
N1 - Publisher Copyright:
© 2018 Association for Computing Machinery.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2018/6/24
Y1 - 2018/6/24
N2 - The architectural differences between ASICs and FPGAs limit the effective performance gains achievable by the application of ASICbased approximation principles for FPGA-based reconfigurable computing systems. This paper presents a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library. Our designs provide higher area, latency and energy gains along with better output accuracy than those offered by the state-of-the-art ASIC-based approximate multipliers. Moreover, compared to the multiplier IP offered by the Xilinx Vivado, our proposed design achieves up to 30%, 53%, and 67% gains in terms of area, latency, and energy, respectively, while incurring an insignificant accuracy loss (on average, below 1% average relative error). Our library of approximate multipliers is open-source and available online at https://cfaed.tudresden. de/pd-downloads to fuel further research and development in this area, and thereby enabling a new research direction for the FPGA community.
AB - The architectural differences between ASICs and FPGAs limit the effective performance gains achievable by the application of ASICbased approximation principles for FPGA-based reconfigurable computing systems. This paper presents a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library. Our designs provide higher area, latency and energy gains along with better output accuracy than those offered by the state-of-the-art ASIC-based approximate multipliers. Moreover, compared to the multiplier IP offered by the Xilinx Vivado, our proposed design achieves up to 30%, 53%, and 67% gains in terms of area, latency, and energy, respectively, while incurring an insignificant accuracy loss (on average, below 1% average relative error). Our library of approximate multipliers is open-source and available online at https://cfaed.tudresden. de/pd-downloads to fuel further research and development in this area, and thereby enabling a new research direction for the FPGA community.
UR - http://www.scopus.com/inward/record.url?scp=85053690223&partnerID=8YFLogxK
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U2 - 10.1145/3195970.3195996
DO - 10.1145/3195970.3195996
M3 - Conference contribution
AN - SCOPUS:85053690223
SN - 9781450357005
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 55th Annual Design Automation Conference, DAC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 55th Annual Design Automation Conference, DAC 2018
Y2 - 24 June 2018 through 29 June 2018
ER -