TY - GEN
T1 - ASCENT
T2 - 43rd International Conference on Computer-Aided Design, ICCAD 2024
AU - Bhandari, Jitendra
AU - Chowdhury, Animesh Basak
AU - Sinanoglu, Ozgur
AU - Garg, Siddharth
AU - Karri, Ramesh
AU - Knechtel, Johann
N1 - Publisher Copyright:
© 2024 Copyright is held by the owner/author(s).
PY - 2025/4/9
Y1 - 2025/4/9
N2 - Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for security arising from the design automation process. That is, automation traditionally prioritizes power, performance, and area (PPA), sidelining security. We propose a “security-first” approach, refining the logic synthesis stage to enhance the overall resilience of PSC countermeasures. We introduce ASCENT, a learning-and-search-based framework that (i) drastically reduces the time for post-design PSC evaluation and (ii) explores the security-vs-PPA design space. Thus, ASCENT enables an efficient exploration of a large number of candidate netlists, leading to an improvement in PSC resilience compared to regular PPA-optimized netlists. ASCENT is up to 120x faster than traditional PSC analysis and yields a 3.11x improvement for PSC resilience of state-of-the-art PSC countermeasures.
AB - Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for security arising from the design automation process. That is, automation traditionally prioritizes power, performance, and area (PPA), sidelining security. We propose a “security-first” approach, refining the logic synthesis stage to enhance the overall resilience of PSC countermeasures. We introduce ASCENT, a learning-and-search-based framework that (i) drastically reduces the time for post-design PSC evaluation and (ii) explores the security-vs-PPA design space. Thus, ASCENT enables an efficient exploration of a large number of candidate netlists, leading to an improvement in PSC resilience compared to regular PPA-optimized netlists. ASCENT is up to 120x faster than traditional PSC analysis and yields a 3.11x improvement for PSC resilience of state-of-the-art PSC countermeasures.
KW - Design-Space Exploration
KW - Hardware Security
KW - Logic Synthesis
KW - Monte Carlo Tree Search
KW - Power Side-Channel
UR - http://www.scopus.com/inward/record.url?scp=105003643751&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=105003643751&partnerID=8YFLogxK
U2 - 10.1145/3676536.3676821
DO - 10.1145/3676536.3676821
M3 - Conference contribution
AN - SCOPUS:105003643751
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 27 October 2024 through 31 October 2024
ER -