ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era

Florian Kriebel; Semeen Rehman; Duo Sun; Muhammad Shafique; Jörg Henkel

doi:10.1145/2593069.2593094

ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era

Florian Kriebel, Semeen Rehman, Duo Sun, Muhammad Shafique, Jörg Henkel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The Dark Silicon provides opportunities to realize Reliability- Heterogeneous Processors with ISA compatible cores having different levels of protection against reliability threats (like soft errors). This paper presents design-time customization of Reliability-Heterogeneous Processors given a set of applications and area constraints. A run-time system adaptively manages the soft error resilience under a given thermal design power (TDP) budget. We synthesize an embedded processor with different levels of protection and present area and power results for a 45nm technology. We illustrate the benefits of adaptive soft error resilience by comparing it with four different state-of-the-Art approaches where we achieve 58%-96% overall system reliability improvements under a tight TDP constraint (corresponding to a 65% dark area).

Original language	English (US)
Title of host publication	DAC 2014 - 51st Design Automation Conference, Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479930173
DOIs	https://doi.org/10.1145/2593069.2593094
State	Published - 2014
Event	51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States Duration: Jun 2 2014 → Jun 5 2014

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Other

Other	51st Annual Design Automation Conference, DAC 2014
Country/Territory	United States
City	San Francisco, CA
Period	6/2/14 → 6/5/14

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

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10.1145/2593069.2593094

Cite this

Kriebel, F., Rehman, S., Sun, D., Shafique, M., & Henkel, J. (2014). ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In DAC 2014 - 51st Design Automation Conference, Conference Proceedings Article 2593094 (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2593069.2593094

ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. / Kriebel, Florian; Rehman, Semeen; Sun, Duo et al.
DAC 2014 - 51st Design Automation Conference, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2014. 2593094 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kriebel, F, Rehman, S, Sun, D, Shafique, M & Henkel, J 2014, ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. in DAC 2014 - 51st Design Automation Conference, Conference Proceedings., 2593094, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., 51st Annual Design Automation Conference, DAC 2014, San Francisco, CA, United States, 6/2/14. https://doi.org/10.1145/2593069.2593094

Kriebel F, Rehman S, Sun D, Shafique M, Henkel J. ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In DAC 2014 - 51st Design Automation Conference, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2014. 2593094. (Proceedings - Design Automation Conference). doi: 10.1145/2593069.2593094

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AB - The Dark Silicon provides opportunities to realize Reliability- Heterogeneous Processors with ISA compatible cores having different levels of protection against reliability threats (like soft errors). This paper presents design-time customization of Reliability-Heterogeneous Processors given a set of applications and area constraints. A run-time system adaptively manages the soft error resilience under a given thermal design power (TDP) budget. We synthesize an embedded processor with different levels of protection and present area and power results for a 45nm technology. We illustrate the benefits of adaptive soft error resilience by comparing it with four different state-of-the-Art approaches where we achieve 58%-96% overall system reliability improvements under a tight TDP constraint (corresponding to a 65% dark area).

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ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era

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