TY - JOUR
T1 - Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis
AU - Garibotti, Rafael
AU - Reagen, Brandon
AU - Shao, Yakun Sophia
AU - Wei, Gu Yeon
AU - Brooks, David
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/10
Y1 - 2018/10
N2 - Recent advances in high-level synthesis (HLS) have enabled an automatic means of generating register-transfer level from high-level specifications without compromising performance. HLS provides substantial improvements to productivity and is a promising solution to designing future heterogeneous chips consisting of dozens of unique IP blocks (i.e., hardware accelerators). Despite their impressive capabilities, HLS tools today are commonly used to target a small subset of workloads, i.e., ones with inordinately regular control flow and memory access patterns. The challenges of achieving high-quality hardware for irregular workloads stems from HLS relying on static analysis. Static analysis is overly conservative when dealing with non-uniform memory access and imbalanced workloads, and identifying the most appropriate parallelizing strategy. In this brief, we propose the use of dynamic analysis to generate higher quality designs using commercial HLS tools. Our evaluations show that with dynamic dependence analysis, HLS designs achieve 3.3 × performance improvement for the sparse matrix-vector multiply benchmark.
AB - Recent advances in high-level synthesis (HLS) have enabled an automatic means of generating register-transfer level from high-level specifications without compromising performance. HLS provides substantial improvements to productivity and is a promising solution to designing future heterogeneous chips consisting of dozens of unique IP blocks (i.e., hardware accelerators). Despite their impressive capabilities, HLS tools today are commonly used to target a small subset of workloads, i.e., ones with inordinately regular control flow and memory access patterns. The challenges of achieving high-quality hardware for irregular workloads stems from HLS relying on static analysis. Static analysis is overly conservative when dealing with non-uniform memory access and imbalanced workloads, and identifying the most appropriate parallelizing strategy. In this brief, we propose the use of dynamic analysis to generate higher quality designs using commercial HLS tools. Our evaluations show that with dynamic dependence analysis, HLS designs achieve 3.3 × performance improvement for the sparse matrix-vector multiply benchmark.
KW - Hardware accelerators
KW - SpMV benchmark
KW - dynamic dependence analysis
KW - high-level synthesis
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U2 - 10.1109/TCSII.2018.2860122
DO - 10.1109/TCSII.2018.2860122
M3 - Article
AN - SCOPUS:85050735454
SN - 1549-7747
VL - 65
SP - 1440
EP - 1444
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 10
M1 - 8421281
ER -