Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (ICs) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed most of the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: 1) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and preexisting IPs); 2) it obfuscates the semantics of an IC before logic synthesis; and 3) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE against state-of-the-art oracle-less attacks.
|Original language||English (US)|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Accepted/In press - 2021|
- IP protection
- Integrated circuits
- Logic gates
- logic locking
- register-transfer level (RTL)
- untrusted foundry.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering