TY - GEN
T1 - ATPG-based cost-effective, secure logic locking
AU - Sengupta, Abhrajit
AU - Nabeel, Mohammed
AU - Yasin, Muhammad
AU - Sinanoglu, Ozgur
PY - 2018/5/29
Y1 - 2018/5/29
N2 - The globalization of IC supply chain lead to the emergence of hardware security threats such as IP piracy, reverse engineering, overbuilding, and hardware Trojans. Among the techniques developed to mitigate these threats, logic locking offers the most versatile protection and is being actively researched. The most recent locking technique SFLL thwarts with provable and quantifiable security all the state-of-the-art attacks including SAT, AppSAT, and the removal attack. However, the implementation cost of SFLL can sometimes be prohibitive, as it lacks an automated framework that explores cost-effective implementation options. In this paper, we show how VLSI testing principles and tools can be adopted to automate critical steps in SFLL and minimize its cost. We propose "SFLL-fault" that utilizes fault injection driven synthesis to efficiently explore design options and ATPG to assess security levels. Our experimental results confirm the efficacy of our strategy; SFLL-fault can reduce the implementation cost by 35% compared to SFLL without compromising security.
AB - The globalization of IC supply chain lead to the emergence of hardware security threats such as IP piracy, reverse engineering, overbuilding, and hardware Trojans. Among the techniques developed to mitigate these threats, logic locking offers the most versatile protection and is being actively researched. The most recent locking technique SFLL thwarts with provable and quantifiable security all the state-of-the-art attacks including SAT, AppSAT, and the removal attack. However, the implementation cost of SFLL can sometimes be prohibitive, as it lacks an automated framework that explores cost-effective implementation options. In this paper, we show how VLSI testing principles and tools can be adopted to automate critical steps in SFLL and minimize its cost. We propose "SFLL-fault" that utilizes fault injection driven synthesis to efficiently explore design options and ATPG to assess security levels. Our experimental results confirm the efficacy of our strategy; SFLL-fault can reduce the implementation cost by 35% compared to SFLL without compromising security.
KW - ATPG
KW - IP piracy
KW - VLSI testing
KW - logic locking
KW - reverse engineering
UR - http://www.scopus.com/inward/record.url?scp=85048363591&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048363591&partnerID=8YFLogxK
U2 - 10.1109/VTS.2018.8368625
DO - 10.1109/VTS.2018.8368625
M3 - Conference contribution
AN - SCOPUS:85048363591
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 1
EP - 6
BT - Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018
PB - IEEE Computer Society
T2 - 36th IEEE VLSI Test Symposium, VTS 2018
Y2 - 22 April 2018 through 25 April 2018
ER -