ATPG-based cost-effective, secure logic locking

Abhrajit Sengupta, Mohammed Nabeel, Muhammad Yasin, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The globalization of IC supply chain lead to the emergence of hardware security threats such as IP piracy, reverse engineering, overbuilding, and hardware Trojans. Among the techniques developed to mitigate these threats, logic locking offers the most versatile protection and is being actively researched. The most recent locking technique SFLL thwarts with provable and quantifiable security all the state-of-the-art attacks including SAT, AppSAT, and the removal attack. However, the implementation cost of SFLL can sometimes be prohibitive, as it lacks an automated framework that explores cost-effective implementation options. In this paper, we show how VLSI testing principles and tools can be adopted to automate critical steps in SFLL and minimize its cost. We propose "SFLL-fault" that utilizes fault injection driven synthesis to efficiently explore design options and ATPG to assess security levels. Our experimental results confirm the efficacy of our strategy; SFLL-fault can reduce the implementation cost by 35% compared to SFLL without compromising security.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781538637746
StatePublished - May 29 2018
Event36th IEEE VLSI Test Symposium, VTS 2018 - San Francisco, United States
Duration: Apr 22 2018Apr 25 2018

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other36th IEEE VLSI Test Symposium, VTS 2018
Country/TerritoryUnited States
CitySan Francisco


  • ATPG
  • IP piracy
  • VLSI testing
  • logic locking
  • reverse engineering

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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