TY - GEN
T1 - AUGER
T2 - 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
AU - Hernandez-Araya, Deykel
AU - Castro-Godinez, Jorge
AU - Shafique, Muhammad
AU - Henkel, Jorg
N1 - Funding Information:
This work was supported in part by the Costa Rica Institute of Technology.
Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/2
Y1 - 2020/2
N2 - In recent years, many approximate arithmetic circuits have been proposed to exploit available error resiliency in a wide set of applications. Approximate adders, multipliers, and dividers reduce their original delay, area, power, or energy, as the accuracy of their results is lowered. Due to the diversity of these approximate units and their potential configurations, selecting one that properly fits t o a s pecific de sign re quires to dispose with a vast number of such units already implemented and characterized. Even to propose new approximate arithmetic circuits, it is required to have existing ones available to perform comparisons. In this paper, we present AUGER, a tool to generate and characterize state-of-the-art approximate arithmetic circuits, providing their RTL implementation and a functional model. We validate our tool by presenting examples of its usage and performing analysis with results it produces. AUGER is released as an open-source contribution.
AB - In recent years, many approximate arithmetic circuits have been proposed to exploit available error resiliency in a wide set of applications. Approximate adders, multipliers, and dividers reduce their original delay, area, power, or energy, as the accuracy of their results is lowered. Due to the diversity of these approximate units and their potential configurations, selecting one that properly fits t o a s pecific de sign re quires to dispose with a vast number of such units already implemented and characterized. Even to propose new approximate arithmetic circuits, it is required to have existing ones available to perform comparisons. In this paper, we present AUGER, a tool to generate and characterize state-of-the-art approximate arithmetic circuits, providing their RTL implementation and a functional model. We validate our tool by presenting examples of its usage and performing analysis with results it produces. AUGER is released as an open-source contribution.
KW - Approximate computing
KW - approximation error
KW - design tools
KW - digital arithmetic
UR - http://www.scopus.com/inward/record.url?scp=85084304988&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85084304988&partnerID=8YFLogxK
U2 - 10.1109/LASCAS45839.2020.9069045
DO - 10.1109/LASCAS45839.2020.9069045
M3 - Conference contribution
AN - SCOPUS:85084304988
T3 - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 25 February 2020 through 28 February 2020
ER -