Automatic verification of sequential circuits using temporal logic

Bhubaneswar Mishra, M Browne, EM Clarke, D Dill

Research output: Chapter in Book/Report/Conference proceeding › Chapter (peer-reviewed) › peer-review

Original language	English (US)
Title of host publication	IEEE tutorial on formal verification of hardware designs
Editors	M Yoeli
Publisher	IEEE Computer Society Press
Pages	166-175
State	Published - 1991

Name	reprint

Cite this

@inbook{ad9e7d1627d5488fb4b01b6b75676033,

title = "Automatic verification of sequential circuits using temporal logic",

author = "Bhubaneswar Mishra and M Browne and EM Clarke and D Dill",

year = "1991",

language = "English (US)",

series = "reprint",

publisher = "IEEE Computer Society Press",

pages = "166--175",

editor = "M Yoeli",

booktitle = "IEEE tutorial on formal verification of hardware designs",

}