Autonomous yet deterministic test of SOC cores

Ozgur Sinanoglu, Alex Orailoglu

Research output: Contribution to journalConference articlepeer-review


Increased core test parallelism translates into reduced SOC test application time; yet the availability of a limited number of tester channels hampers this parallelism. Furthermore, the test vectors to be delivered into core scan chains need to be stored in the tester memory, imposing considerable costs on SOC tests. In this paper, we propose an SOC test methodology delivering all the benefits of core self-test, while ensuring fault coverage levels identical to those attained in deterministic test. In the proposed methodology, a single LFSR broadcasts pseudo-random patterns to each core; the LFSR patterns are transformed into the actual test vectors of a core while they are being shifted into the core scan chain. The transformation is realized through the logic gates inserted between the core scan cells. The efficacy and the cost-effectiveness of the proposed methodology reflects into significantly reduced test costs.

Original languageEnglish (US)
Pages (from-to)1359-1368
Number of pages10
JournalProceedings - International Test Conference
StatePublished - 2004
EventProceedings - International Test Conference 2004 - Charlotte, NC, United States
Duration: Oct 26 2004Oct 28 2004

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


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