Increased core test parallelism translates into reduced SOC test application time; yet the availability of a limited number of tester channels hampers this parallelism. Furthermore, the test vectors to be delivered into core scan chains need to be stored in the tester memory, imposing considerable costs on SOC tests. In this paper, we propose an SOC test methodology delivering all the benefits of core self-test, while ensuring fault coverage levels identical to those attained in deterministic test. In the proposed methodology, a single LFSR broadcasts pseudo-random patterns to each core; the LFSR patterns are transformed into the actual test vectors of a core while they are being shifted into the core scan chain. The transformation is realized through the logic gates inserted between the core scan cells. The efficacy and the cost-effectiveness of the proposed methodology reflects into significantly reduced test costs.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Applied Mathematics