AVF analysis acceleration via hierarchical fault pruning

Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. In response, designers have introduced various methodologies that allow AVF calculation within reasonable time, at the cost of some loss of accuracy. In this paper, we present a method for calculating the AVF of design elements -using Statistical Fault Injection (SFI)- with equal accuracy but several orders of magnitude faster than traditional SFI techniques. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate the AVF numbers. The presented method has been applied on an Intel microprocessor, where experimental results corroborate its ability to achieve great speed-up while maintaining perfect accuracy in calculating AVF.

Original languageEnglish (US)
Title of host publicationProceedings - 16th IEEE European Test Symposium, ETS 2011
Number of pages6
StatePublished - 2011
Event16th IEEE European Test Symposium, ETS 2011 - Trondheim, Norway
Duration: May 23 2011May 27 2011

Publication series

NameProceedings - 16th IEEE European Test Symposium, ETS 2011


Other16th IEEE European Test Symposium, ETS 2011

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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