Behavior Analysis of CMOS D Flip-Flops

Jonathan H.J. Chao; Cesar A. Johnston

doi:10.1109/JSSC.1989.572637

Behavior Analysis of CMOS D Flip-Flops

Jonathan H.J. Chao, Cesar A. Johnston

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we analyze two D flip-flops (DFF‘s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a twophase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

Original language	English (US)
Pages (from-to)	1454-1458
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1989.572637
State	Published - Oct 1989

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1989.572637

Cite this

@article{249c8c0cbba146708b1c603c1498e770,

title = "Behavior Analysis of CMOS D Flip-Flops",

abstract = "In this paper, we analyze two D flip-flops (DFF{\textquoteleft}s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a twophase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.",

author = "Chao, {Jonathan H.J.} and Johnston, {Cesar A.}",

year = "1989",

month = oct,

doi = "10.1109/JSSC.1989.572637",

language = "English (US)",

volume = "24",

pages = "1454--1458",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Behavior Analysis of CMOS D Flip-Flops

AU - Chao, Jonathan H.J.

AU - Johnston, Cesar A.

PY - 1989/10

Y1 - 1989/10

N2 - In this paper, we analyze two D flip-flops (DFF‘s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a twophase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

AB - In this paper, we analyze two D flip-flops (DFF‘s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a twophase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

UR - http://www.scopus.com/inward/record.url?scp=0024749530&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024749530&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1989.572637

DO - 10.1109/JSSC.1989.572637

M3 - Article

AN - SCOPUS:0024749530

SN - 0018-9200

VL - 24

SP - 1454

EP - 1458

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 5

ER -

Behavior Analysis of CMOS D Flip-Flops

Abstract

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