Behavior Analysis of CMOS D Flip-Flops

Jonathan H.J. Chao, Cesar A. Johnston

Research output: Contribution to journalArticlepeer-review


In this paper, we analyze two D flip-flops (DFF‘s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a twophase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

Original languageEnglish (US)
Pages (from-to)1454-1458
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - Oct 1989

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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