TY - GEN
T1 - Benchmarking Security Closure of Physical Layouts
AU - Knechtel, Johann
AU - Gopinath, Jayanth
AU - Ashraf, Mohammed
AU - Bhandari, Jitendra
AU - Sinanoglu, Ozgur
AU - Karri, Ramesh
N1 - Funding Information:
This work was supported in parts by the Center for Cyber Security (CCS) at NYU New York/Abu Dhabi (NYU/NYUAD). We would like to thank the ISPD committee for featuring this contest, and David Chinnery, Gracieli Posser in particular for interaction and guidance. We also like to thank Sumesh Manjunath Ramesh (NYUAD) for sharing HDL codes for the PRESENT and SPARX crypto cores, and Mohammed Nabeel (NYUAD) for additional help with the evaluation backend.
Publisher Copyright:
© 2022 ACM.
PY - 2022/4/13
Y1 - 2022/4/13
N2 - Computer-aided design (CAD) tools mainly optimize for power, performance, and area (PPA). However, given a large number of serious hardware-security threats that are emerging, future CAD flows must also incorporate techniques for designing secure integrated circuits (ICs). In fact, the stakes are quite high for IC vendors and design companies, as security risks that are not addressed during design time will inevitably be exploited in the field, where vulnerabilities are almost impossible to fix. However, there is currently little to no experience related to designing secure ICs available within the CAD community. For the very first time, this contest seeks to actively engage with the community to close this gap. The theme of this contest is security closure of physical layouts, that is, hardening the physical layouts at design time against threats that are executed post-design time. More specifically, this contest is focused on selected and seminal threats that, once taken in, are relatively simple to approach and mitigate through means of physical design: Trojan insertion and probing as well as fault injection. Acting as security engineers, contest participants will iteratively and proactively evaluate and fix the vulnerabilities of provided benchmark layouts. Benchmarks and submissions are based on the generic DEF format and related files. Thus, participants are free to use any physical-design tools of their choice, helping us to open up the contest to the community at large.
AB - Computer-aided design (CAD) tools mainly optimize for power, performance, and area (PPA). However, given a large number of serious hardware-security threats that are emerging, future CAD flows must also incorporate techniques for designing secure integrated circuits (ICs). In fact, the stakes are quite high for IC vendors and design companies, as security risks that are not addressed during design time will inevitably be exploited in the field, where vulnerabilities are almost impossible to fix. However, there is currently little to no experience related to designing secure ICs available within the CAD community. For the very first time, this contest seeks to actively engage with the community to close this gap. The theme of this contest is security closure of physical layouts, that is, hardening the physical layouts at design time against threats that are executed post-design time. More specifically, this contest is focused on selected and seminal threats that, once taken in, are relatively simple to approach and mitigate through means of physical design: Trojan insertion and probing as well as fault injection. Acting as security engineers, contest participants will iteratively and proactively evaluate and fix the vulnerabilities of provided benchmark layouts. Benchmarks and submissions are based on the generic DEF format and related files. Thus, participants are free to use any physical-design tools of their choice, helping us to open up the contest to the community at large.
KW - contest
KW - fault-injection attacks
KW - hardware security
KW - physical design
KW - probing attacks
KW - read-out attacks
KW - security closure
KW - trojans
UR - http://www.scopus.com/inward/record.url?scp=85128656727&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85128656727&partnerID=8YFLogxK
U2 - 10.1145/3505170.3511046
DO - 10.1145/3505170.3511046
M3 - Conference contribution
AN - SCOPUS:85128656727
T3 - Proceedings of the International Symposium on Physical Design
SP - 221
EP - 228
BT - ISPD 2022 - Proceedings of the 2022 International Symposium on Physical Design
PB - Association for Computing Machinery
T2 - 31st ACM International Symposium on Physical Design, ISPD 2022
Y2 - 27 March 2022 through 30 March 2022
ER -