On-chip photonic waveguides have been proposed as a feasible replacement for the long interconnects that cause speed and power bottlenecks. Along with recent advancements in nanophotonic technologies, we believe that combining on-chip waveguides with high-radix Network on Chip (NoC) topologies is a promising way to improve NoC performance. In this paper, we propose the BLOCON (BufferLess phOtonic ClOs Network) to exploit silicon photonics. We propose a scheduling algorithm named Sustained and Informed Dual Round-Robin Matching (SIDRRM) to solve the output contention problem, and a path allocation scheme named Distributed and Informed Path Allocation (DIPA) to solve the Clos network routing problem. In the simulation results, we show that with SIDRRM and DIPA, BLOCON improves the delay and power performance of the compared electrical and photonic NoC architectures over synthetic traffic patterns and SPLASH-2 traces.