TY - GEN
T1 - Can flexible, domain specific programmable logic prevent IP theft?
AU - Cui, Xiaotong
AU - Wu, Kaijie
AU - Garg, Siddharth
AU - Karri, Ramesh
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/10/25
Y1 - 2016/10/25
N2 - Fab-less design houses are outsourcing fabrication to third-party foundries to reduce costs. However, this has security consequences including intellectual property (IP) theft and piracy. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft and piracy. However, many obfuscation techniques through redesign or split manufacturing are costly in terms of manufacturing. We propose a High Level Synthesis and Analysis (HLSA) approach that leverages embedded programmable logic (EPL) to hide sensitive parts of the IP from a rogue foundry or a rogue actor in a foundry. While EPL was originally proposed to make the SoC programmable, we show that it can help a designer to thwart IP theft. Careful insertion of EPL increases the resistance to reverse engineering while managing the power consumption, area overhead and performance penalty. Our proposed security-aware HLSA design flow enables designers to explore this trade-off.
AB - Fab-less design houses are outsourcing fabrication to third-party foundries to reduce costs. However, this has security consequences including intellectual property (IP) theft and piracy. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft and piracy. However, many obfuscation techniques through redesign or split manufacturing are costly in terms of manufacturing. We propose a High Level Synthesis and Analysis (HLSA) approach that leverages embedded programmable logic (EPL) to hide sensitive parts of the IP from a rogue foundry or a rogue actor in a foundry. While EPL was originally proposed to make the SoC programmable, we show that it can help a designer to thwart IP theft. Careful insertion of EPL increases the resistance to reverse engineering while managing the power consumption, area overhead and performance penalty. Our proposed security-aware HLSA design flow enables designers to explore this trade-off.
KW - IP theft
KW - SoC
KW - embedded programmable logic
KW - high level synthesis and analysis
UR - http://www.scopus.com/inward/record.url?scp=84999231125&partnerID=8YFLogxK
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U2 - 10.1109/DFT.2016.7684088
DO - 10.1109/DFT.2016.7684088
M3 - Conference contribution
AN - SCOPUS:84999231125
T3 - 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
SP - 153
EP - 157
BT - 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
Y2 - 19 September 2016 through 20 September 2016
ER -