Capacitor-less Dual-mode All-Digital LDO with ΔΣ-modulation-based Ripple Reduction

Muhammad Abrar Akram, Wook Hong, Sohmyung Ha, In Chul Hwang

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a capacitor-less digital low-dropout (DLDO) regulator, which has low steady-state voltage ripples (VRIPP) and low output noise, suitable for driving analog circuits in system-on-chip devices. To reduce VRIPP, a steady-state control based on ΔΣ modulation and a clock multiplication technique are proposed. Thanks to the ΔΣ operation, the proposed DLDO generates noise-shaped output voltage (VOUT), reducing VRIPP and improving its noise performance without using an output capacitor. The ΔΣ-modulator-based controller is activated just during the steady state, triggered by a lock detector, which continuously tracks VOUT and compares it to a reference VREF. During the steady state, a cyclic time-to-pulse converter and a clock combiner generate an oversampling clock for the controller. The proposed DLDO was fabricated in a 110-nm CMOS process with an active area of 0.07 mm2. The measurement results demonstrate that at VOUT = 0.5 V, VDD = 0.6 V, and ILOAD = 500 μA, the proposed DLDO achieves <1 mV of VRIPP, 17.5 dB of power supply rejection (PSR) at 1 MHz, and -151 V2rms/Hz (dB) of power-spectral density at 51.2 kHz. Furthermore, the proposed DLDO achieves 99.77% of current efficiency and 0.25 mV/mA of load regulation while driving the maximum ILOAD of 40 mA.

Original languageEnglish (US)
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
DOIs
StateAccepted/In press - 2021

Keywords

  • ΔΣ modulator
  • capacitor-less
  • Capacitors
  • Clocks
  • Detectors
  • Digital Low-dropout regulator (LDO)
  • Laser mode locking
  • Modulation
  • power-supply rejection (PSR)
  • Steady-state
  • steady-state voltage ripples
  • supply noise sensitivity.
  • Voltage control

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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