Abstract
We consider the problem of generating layouts of multi-level networks, in particular, switching, sorting, and interconnection networks, as compactly as possible on VLSI grids. Besides traditional interest in these problems motivated by interconnection topologies in parallel computing and switching circuits in telecommunications, there is renewed interest in such layouts in the context of ATM (Asynchronous Transfer Mode) switches. Our results improve on the existing area bounds for these networks by factors of up to three.
Original language | English (US) |
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Title of host publication | Conference Proceedings of the Annual ACM Symposium on Theory of Computing |
Publisher | ACM |
Pages | 455-463 |
Number of pages | 9 |
State | Published - 1999 |
Event | Proceedings of the 1999 31st Annual ACM Symposium on Theory of Computing - FCRC '99 - Atlanta, GA, USA Duration: May 1 1999 → May 4 1999 |
Other
Other | Proceedings of the 1999 31st Annual ACM Symposium on Theory of Computing - FCRC '99 |
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City | Atlanta, GA, USA |
Period | 5/1/99 → 5/4/99 |
ASJC Scopus subject areas
- Software