Compact hardware architectures for BLAKE and LAKE hash functions

Jianzhou Li; Ramesh Karri

doi:10.1109/ISCAS.2010.5537063

Compact hardware architectures for BLAKE and LAKE hash functions

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

BLAKE, one of SHA-3 candidates, and LAKE hash functions show the characteristic that the block length of the internal state is double its initial and final states, which means more registers are required for the implementation of the hash functions. In this paper, we explore shift register based compact hardware architectures for the two hash functions. This includes the 32-, 64-, and 128-bit datapath architectures for BLAKE. We provide post Place&Route performance results on both ASIC and FPGA platforms. The power consumption for each design is also given. Our results show that BLAKE has comparable performance when compared with the previous standard hash function of Whirlpool and less performance advantages over SHA-256. The results also indicate that BLAKE outperforms LAKE in the hardware implementation.

Original language	English (US)
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	2107-2110
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537063
State	Published - 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: May 30 2010 → Jun 2 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	5/30/10 → 6/2/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISCAS.2010.5537063

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Li, J., & Karri, R. (2010). Compact hardware architectures for BLAKE and LAKE hash functions. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 2107-2110). Article 5537063 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537063

Compact hardware architectures for BLAKE and LAKE hash functions. / Li, Jianzhou; Karri, Ramesh.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 2107-2110 5537063 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, J & Karri, R 2010, Compact hardware architectures for BLAKE and LAKE hash functions. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537063, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 2107-2110, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 5/30/10. https://doi.org/10.1109/ISCAS.2010.5537063

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Compact hardware architectures for BLAKE and LAKE hash functions

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