Compacting test responses for deeply embedded SoC cores

Ozgur Sinanoglu; Alex Orailoglu

doi:10.1109/MDT.2003.1214349

Compacting test responses for deeply embedded SoC cores

Research output: Contribution to journal › Article › peer-review

Abstract

A fault-model-dependent compaction methodology that delivers the lowest possible test bandwidth with no aliasing of the modeled faults is proposed. This methodology is also computationally efficient because the aliasing analysis handles only a small subset of the faults. Subsequently, the proposed methodology is extended to scan-based cores.

Original language	English (US)
Pages (from-to)	22-30
Number of pages	9
Journal	IEEE Design and Test of Computers
Volume	20
Issue number	4
DOIs	https://doi.org/10.1109/MDT.2003.1214349
State	Published - Jul 2003

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MDT.2003.1214349

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title = "Compacting test responses for deeply embedded SoC cores",

abstract = "A fault-model-dependent compaction methodology that delivers the lowest possible test bandwidth with no aliasing of the modeled faults is proposed. This methodology is also computationally efficient because the aliasing analysis handles only a small subset of the faults. Subsequently, the proposed methodology is extended to scan-based cores.",

author = "Ozgur Sinanoglu and Alex Orailoglu",

year = "2003",

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JO - IEEE Design and Test of Computers

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Compacting test responses for deeply embedded SoC cores

Abstract

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