A fault-model-dependent compaction methodology that delivers the lowest possible test bandwidth with no aliasing of the modeled faults is proposed. This methodology is also computationally efficient because the aliasing analysis handles only a small subset of the faults. Subsequently, the proposed methodology is extended to scan-based cores.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Design and Test of Computers|
|State||Published - Jul 2003|
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering