This work investigates the joint impact of device variability and transistor aging on the data integrity of SRAM cells implemented using 22 FDSOI. Our analysis is based on well-calibrated TCAD simulations that reproduce measurements from a commercial 22nm FDSOI technology node. The calibrations are done against measurement data for both I-V characteristics and variability data. We perform error analysis for SRAMs during hold and read operations under three different scenarios: (i) Fresh: time-zero variation (PV) alone caused by manufacturing variability, (ii) Aged: combined impact of PV and aging-induced increase in the transistor threshold voltage (VTH) at the room temperature, (iii) Aged@85°C: combined impact of PV and transistor aging but at an elevated temperature of 85°C. Further, we explore how SRAM errors are exacerbated when the voltage is scaled down due to the reductions in noise margins. All error analyses were accurately performed in TCAD mixed-mode simulations for a complete 6-T SRAM cell. Finally, to investigate further how such errors impact the system level, we explore the corresponding induced accuracy drop in Deep Neural Networks (DNNs). Different quantized NNs are studied, and their sensitivity to errors in weights and activations is also explored. We demonstrate that short-term aging (i.e., when aging effects are combined with voltage scaling) results in a noticeable accuracy drop when ResNet20 and ResNet18 DNN models are examined on the CIFAR100 and Imagenet datasets, respectively.