Abstract
The authors present a flexible methodology for compiling an algorithmic description into an equivalent fault-tolerant VLSI circuit and a CAD framework embodying this methodology. Experimental designs illustrate and validate algorithms for automated synthesis of ICs featuring either self-recovery capability or enhanced reliability.
Original language | English (US) |
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Pages (from-to) | 88-96 |
Number of pages | 9 |
Journal | IEEE Design and Test of Computers |
Volume | 13 |
Issue number | 3 |
DOIs | |
State | Published - Sep 1996 |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering