The authors present a flexible methodology for compiling an algorithmic description into an equivalent fault-tolerant VLSI circuit and a CAD framework embodying this methodology. Experimental designs illustrate and validate algorithms for automated synthesis of ICs featuring either self-recovery capability or enhanced reliability.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Design and Test of Computers|
|State||Published - Sep 1996|
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering