Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers

R. Karri, K. Wu, P. Mishra, Y. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages579-584
Number of pages6
StatePublished - 2001
Event38th Design Automation Conference - Las Vegas, NV, United States
Duration: Jun 18 2001Jun 22 2001

Other

Other38th Design Automation Conference
CountryUnited States
CityLas Vegas, NV
Period6/18/016/22/01

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Fingerprint Dive into the research topics of 'Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers'. Together they form a unique fingerprint.

  • Cite this

    Karri, R., Wu, K., Mishra, P., & Kim, Y. (2001). Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers. In Proceedings - Design Automation Conference (pp. 579-584)