Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim

Research output: Contribution to journalArticle

Abstract

Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, performance penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

Original languageEnglish (US)
Pages (from-to)1509-1517
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume21
Issue number12
DOIs
StatePublished - Dec 2002

Keywords

  • AES
  • CED
  • Cryptanalysis
  • Cryptography
  • Fault based
  • RC6
  • Rijndael
  • Serpent
  • Side channel
  • Symmetric encryption
  • Twofish

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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