Abstract
A methodology for behavioral synthesis of an important class of reconfigurable data path designs called configurable spare processors is presented. This configurable spare efficiently implements any of k applications and can be configured to substitute for a faulty processor implementing one of these k applications. Three important techniques targeting configurable spare processor synthesis are also presented.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 295-303 |
| Number of pages | 9 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT'96 - Boston, MA, USA Duration: Nov 6 1996 → Nov 8 1996 |
Other
| Other | Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT'96 |
|---|---|
| City | Boston, MA, USA |
| Period | 11/6/96 → 11/8/96 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering