The increasing size and complexity of integrated circuits result in high test costs due to the consequent expansion of test data. Although test-vector compression and response compaction are effective solutions to the problem of test time and data volume, scan architectures with localised implementation of decompression and compaction fail to adapt well to the varying sizes of compatible scan cell groups. A scan network is presented here that embeds expansions and compactions in a distributed manner, adapting perfectly to the varying sizes of compatible scan-cell groups in different regions of the design. We conduct a stimulus delivery and response collection analysis to identify the particularities of the scan-network implementation, which provides a minimal scan depth while preserving test quality. The proposed methodology implements the scan network by also accounting for the physical position of the scan cells, delivering a practical solution for realistic integrated circuits. The experimental results also confirm the efficacy of the proposed approach.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering