CT-Cache: Compressed tag-driven cache architecture

Haeyoon Cho, Joonho Kong, Arslan Munir, Naresh Kumar Giri

Research output: Chapter in Book/Report/Conference proceedingConference contribution


One of the most challenging problems in designing large caches is to devise efficient cache tag storage. Typical large last-level caches often require tens of megabytes of tag storage. Consequently, this large tag storage leads to high latency and energy consumption for a cache tag access, which adversely affect system performance and energy efficiency. In this paper, we propose CT-Cache that exploits the similarity in upper cache tag bits. Our proposed CT-Cache decouples a tag storage into a global tag table and delta tag arrays. The global tag table is a small fully-Associative buffer that stores upper tag patterns, which can be shared between multiple cache lines, while the delta tag array stores lower tag bits for each cache line. By avoiding the redundant storage, the CT-Cache significantly reduces the cache tag storage size, which in turn reduces latency and energy consumption of a cache tag access. Evaluation results reveal that the CT-Cache reduces tag storage size by 87.8%, which significantly reduces tag access latency and energy. Owing to the tag storage reduction, the CT-Cache improves performance by 4.7%~16.2% and reduces last-level cache and main memory energy consumption by 20.0%~29.7% compared to the conventional caches that use non-compressed tag storage.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
PublisherIEEE Computer Society
Number of pages6
ISBN (Print)9781538670996
StatePublished - Aug 7 2018
Event17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 - Hong Kong, Hong Kong
Duration: Jul 9 2018Jul 11 2018

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477


Conference17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
Country/TerritoryHong Kong
CityHong Kong


  • Cache architecture
  • Energy efficiency
  • Last-Level cache
  • Locality
  • Performance
  • Tag compression

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering


Dive into the research topics of 'CT-Cache: Compressed tag-driven cache architecture'. Together they form a unique fingerprint.

Cite this