TY - GEN
T1 - Customized locking of IP blocks on a multi-million-gate SoC
AU - Sengupta, Abhrajit
AU - Nabeel, Mohammed
AU - Ashraf, Mohammed
AU - Sinanoglu, Ozgur
N1 - Funding Information:
This work is partially sponsored by the Defense Advanced Research Projects Agency (DARPA) OMG program and the New York University/New York University Abu Dhabi (NYU/ NYUAD) Center for Cyber Security (CCS).
Publisher Copyright:
© 2018 ACM.
PY - 2018/11/5
Y1 - 2018/11/5
N2 - Reliance on off-site untrusted fabrication facilities has given rise to several threats such as intellectual property (IP) piracy, overbuilding and hardware Trojans. Logic locking is a promising defense technique against such malicious activities that is effected at the silicon layer. Over the past decade, several logic locking defenses and attacks have been presented, thereby, enhancing the state-of-the-art. Nevertheless, there has been little research aiming to demonstrate the applicability of logic locking with large-scale multi-million-gate industrial designs consisting of multiple IP blocks with different security requirements. In this work, we take on this challenge to successfully lock a multi-million-gate system-on-chip (SoC) provided by DARPA by taking it all the way to GDSII layout. We analyze how specific features, constraints, and security requirements of an IP block can be leveraged to lock its functionality in the most appropriate way. We show that the blocks of an SoC can be locked in a customized manner at 0.5%, 15.3%, and 1.5% chip-level overhead in power, performance, and area, respectively.
AB - Reliance on off-site untrusted fabrication facilities has given rise to several threats such as intellectual property (IP) piracy, overbuilding and hardware Trojans. Logic locking is a promising defense technique against such malicious activities that is effected at the silicon layer. Over the past decade, several logic locking defenses and attacks have been presented, thereby, enhancing the state-of-the-art. Nevertheless, there has been little research aiming to demonstrate the applicability of logic locking with large-scale multi-million-gate industrial designs consisting of multiple IP blocks with different security requirements. In this work, we take on this challenge to successfully lock a multi-million-gate system-on-chip (SoC) provided by DARPA by taking it all the way to GDSII layout. We analyze how specific features, constraints, and security requirements of an IP block can be leveraged to lock its functionality in the most appropriate way. We show that the blocks of an SoC can be locked in a customized manner at 0.5%, 15.3%, and 1.5% chip-level overhead in power, performance, and area, respectively.
KW - IP piracy
KW - VLSI testing
KW - logic locking
KW - system-on-chip
UR - http://www.scopus.com/inward/record.url?scp=85058177958&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85058177958&partnerID=8YFLogxK
U2 - 10.1145/3240765.3243467
DO - 10.1145/3240765.3243467
M3 - Conference contribution
AN - SCOPUS:85058177958
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 37th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018
Y2 - 5 November 2018 through 8 November 2018
ER -