As Dennard's scaling stops mainly due to supply voltage limits, power densities rapidly increase on the chip. Hence, a significant amount of on-chip resources needs to stay dark, i.e., power-gated, in order to avoid thermal emergencies. This phenomenon is known in the literature as dark silicon. Conventional resource management techniques allocate the cores of the chip to the applications, without considering the dark silicon phenomenon. In this chapter, we discuss a dark silicon aware resource management technique that aims at maximizing the overall system performance under a temperature constraint. To achieve its goal, this technique determines the number of active (power-on) cores that should be allocated to each application and the voltage and frequency level of these cores. Additionally, it takes into account the instruction-level parallelism (ILP) and the thread-level parallelism (TLP) of the applications during its decision-making process. Moreover, the presented technique selects the positioning of dark cores such that they facilitate dissipating the generated heat on the active cores. That, in turn, reduces the temperature of the active cores and might allow to increase their voltage and frequency levels leading to further performance improvement. The evaluation of this technique shows its ability to improve the performance with an average of 34% compared to a state-of-the-art technique of thermal-aware performance maximization.