TY - JOUR
T1 - Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip
AU - Haq, Syed Asrar Ul
AU - Gizzini, Abdul Karim
AU - Shrey, Shakti
AU - Darak, Sumit J.
AU - Saurabh, Sneh
AU - Chafii, Marwa
N1 - Funding Information:
The work of Sumit J. Darak was supported by the Department of Science and Technology-Science and Engineering Research Board (DST-SERB), Government of India, through the Core Research Grant (CRG).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2023/7/1
Y1 - 2023/7/1
N2 - Reliable and fast channel estimation is crucial for next-generation wireless networks supporting a wide range of vehicular and low-latency services. Recently, deep learning (DL)-based channel estimation has been explored as an efficient alternative to conventional least-square (LS) and linear minimum mean square error (LMMSE) approaches. Most of these DL approaches have not been realized on system on chip (SoC), and preliminary study shows that their complexity exceeds the complexity of the entire physical layer (PHY). The high latency of DL is another concern. This article considers the design and implementation of deep neural network (DNN) augmented LS (LSDNN)-based channel estimation for preamble-based orthogonal frequency-division multiplexing (OFDM) PHY on SoC. We demonstrate the gain in performance compared with the conventional LS and LMMSE approaches. Via software-hardware codesign, word-length optimization, and reconfigurable architectures, we demonstrate the superiority of the LSDNN over LS and LMMSE for a wide range of signal-to-noise ratio (SNR), number of pilots, preamble types, and wireless channels. Furthermore, we evaluate the performance, power, and area (PPA) of the LS and LSDNN application-specific integrated circuit (ASIC) implementations in 45-nm technology. We demonstrate that word-length optimization can substantially improve PPA for the proposed architecture in ASIC implementations.
AB - Reliable and fast channel estimation is crucial for next-generation wireless networks supporting a wide range of vehicular and low-latency services. Recently, deep learning (DL)-based channel estimation has been explored as an efficient alternative to conventional least-square (LS) and linear minimum mean square error (LMMSE) approaches. Most of these DL approaches have not been realized on system on chip (SoC), and preliminary study shows that their complexity exceeds the complexity of the entire physical layer (PHY). The high latency of DL is another concern. This article considers the design and implementation of deep neural network (DNN) augmented LS (LSDNN)-based channel estimation for preamble-based orthogonal frequency-division multiplexing (OFDM) PHY on SoC. We demonstrate the gain in performance compared with the conventional LS and LMMSE approaches. Via software-hardware codesign, word-length optimization, and reconfigurable architectures, we demonstrate the superiority of the LSDNN over LS and LMMSE for a wide range of signal-to-noise ratio (SNR), number of pilots, preamble types, and wireless channels. Furthermore, we evaluate the performance, power, and area (PPA) of the LS and LSDNN application-specific integrated circuit (ASIC) implementations in 45-nm technology. We demonstrate that word-length optimization can substantially improve PPA for the proposed architecture in ASIC implementations.
KW - Application-specific integrated circuit (ASIC)
KW - channel estimation
KW - deep learning (DL)
KW - field-programmable gate array (FPGA)
KW - hardware-software codesign
KW - least-square (LS)
KW - linear minimum mean square error (LMMSE)
KW - system on chip (SoC)
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U2 - 10.1109/TVLSI.2023.3274555
DO - 10.1109/TVLSI.2023.3274555
M3 - Article
AN - SCOPUS:85160272704
SN - 1063-8210
VL - 31
SP - 1026
EP - 1038
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
ER -