Delay-bound guarantee in combined input-output buffered switches

CIOB (Combined Input-Output Buffered) switches with a moderate speedup have been widely considered as the most feasible solution for large-capacity switches. In this paper, we adopt the hierarchical link sharing (HLS) algorithm in non-blocking CIOB switches to guarantee delay bound that is independent of the switch size. We also propose a feasible architecture to implement the HLS algorithm in the switch, which can accommodate the packet carried over a 10 G bps line without a speedup requirement. Furthermore, we design a new Serial Comparator to find minimum time-stamp values.