Delay Prediction for ASIC HLS: Comparing Graph-based and Non-Graph-based Learning Models

Sayandip De, Muhammad Shafique, Henk Corporaal

Research output: Contribution to journalArticlepeer-review

Abstract

While High-level Synthesis (HLS) tools offer faster design of hardware accelerators with different area vs. delay trade-offs, HLS-based delay estimates often deviate significantly from results obtained from ASIC logic synthesis (LS) tools. Current HLS tools rely on simple additive delay models which fail to capture the downstream optimizations performed during logic synthesis and technology mapping. Inaccurate delay estimates prevent fast and accurate design-space exploration without performing time-consuming logic synthesis tasks. In this work, we exploit different machine learning models which automatically learn to map the different downstream optimizations onto the HLS critical paths. In particular, we compare graph-based and non-graph-based learning models to investigate their efficacy, devise hybrid models to get the best of the both worlds. To carry out our learning-assisted methodology, we create a dataset of different HLS benchmarks and develop an automated framework, which extends a commercial HLS toolchain, to extract essential information from LS critical path and automatically matches this information to HLS path. This is a non-trivial task to perform manually due to difference in level of abstractions. Finally, we train proposed hybrid models through inductive learning and integrate them in the commercial HLS toolchain to improve delay prediction accuracy. Experimental results demonstrate significant improvements in delay estimation accuracy across a wide variety of benchmark designs. We demonstrate that the graph-based models can infer essential structural features from the input design, while incorporating them into traditional non-graph-based models can significantly improve the model accuracy. Such hybrid models can improve delay prediction accuracy by 93% compared to simple additive models and provide 175× speedup compared to LS. Furthermore, we discuss key insights from our experiments, identifying the influence of different HLS features on model performance.

Original languageEnglish (US)
Pages (from-to)1
Number of pages1
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOIs
StateAccepted/In press - 2022

Keywords

  • Adders
  • Additives
  • Delays
  • Field programmable gate arrays
  • Optimization
  • Predictive models
  • Task analysis

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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