TY - GEN
T1 - DeMAS
T2 - 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
AU - Prabakaran, Bharath Srinivas
AU - Rehman, Semeen
AU - Hanif, Muhammad Abdullah
AU - Ullah, Salim
AU - Mazaheri, Ghazal
AU - Kumar, Akash
AU - Shafique, Muhammad
N1 - Publisher Copyright:
© 2018 EDAA.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2018/4/19
Y1 - 2018/4/19
N2 - The current state-of-the-art approximate adders are mostly ASIC-based, i.e., they focus solely on gate and/or transistor level approximations (e.g., through circuit simplification or truncation) to achieve area, latency, power and/or energy savings at the cost of accuracy loss. However, when these designs are synthesized for FPGA-based systems, they do not offer similar reductions in area, latency and power/energy due to the underlying architectural differences between ASICs and FPGAs. In this paper, we present a novel generic design methodology to synthesize and implement approximate adders for any FPGA-based system by considering the underlying resources and architectural differences. Using our methodology, we have designed, analyzed and presented eight different multi-bit adder architectures. Compared to the 16-bit accurate adder, our designs are successful in achieving area, latency and power-delay product gains of 50%, 38%, and 53%, respectively. We also compare our approximate adders to state-of-the-art approximate adders specialized for ASIC and FPGA fabrics and demonstrate the benefits of our approach. We will make the RTL and behavioral models of our and state-of-the-art designs open-source at https://sourceforge.net/projects/approxfpgas/ to further fuel the research and development in the FPGA community and to ensure reproducible research.
AB - The current state-of-the-art approximate adders are mostly ASIC-based, i.e., they focus solely on gate and/or transistor level approximations (e.g., through circuit simplification or truncation) to achieve area, latency, power and/or energy savings at the cost of accuracy loss. However, when these designs are synthesized for FPGA-based systems, they do not offer similar reductions in area, latency and power/energy due to the underlying architectural differences between ASICs and FPGAs. In this paper, we present a novel generic design methodology to synthesize and implement approximate adders for any FPGA-based system by considering the underlying resources and architectural differences. Using our methodology, we have designed, analyzed and presented eight different multi-bit adder architectures. Compared to the 16-bit accurate adder, our designs are successful in achieving area, latency and power-delay product gains of 50%, 38%, and 53%, respectively. We also compare our approximate adders to state-of-the-art approximate adders specialized for ASIC and FPGA fabrics and demonstrate the benefits of our approach. We will make the RTL and behavioral models of our and state-of-the-art designs open-source at https://sourceforge.net/projects/approxfpgas/ to further fuel the research and development in the FPGA community and to ensure reproducible research.
KW - Adders
KW - Approximate Computing
KW - Area
KW - CAD
KW - Design Flow
KW - Efficiency
KW - FPGA
KW - LUTs
KW - Optimization
KW - Performance
KW - Power
UR - http://www.scopus.com/inward/record.url?scp=85048786737&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048786737&partnerID=8YFLogxK
U2 - 10.23919/DATE.2018.8342140
DO - 10.23919/DATE.2018.8342140
M3 - Conference contribution
AN - SCOPUS:85048786737
T3 - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
SP - 917
EP - 920
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 19 March 2018 through 23 March 2018
ER -