Design and analysis of enhanced Abacus switch

J. S. Park; H. Jonathan Chao

doi:10.1016/S0140-3664(01)00425-X

Design and analysis of enhanced Abacus switch

J. S. Park, H. Jonathan Chao

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Combined input-output buffering with a moderate speedup for internal switch fabric has been considered as the most feasible solution to build large-capacity packet switches. This paper describes several schemes to further scale up our previously proposed Abacus switch [IEEE J. Select. Areas Commun. 15 (1997) 830] to multiple terabit per second. The Abacus switch implements the arbiter in a distributed manner, allowing the switch to be scaled in both the port speed and the switch capacity. The switch can be easily implemented using crosspoint switch chips with self-routing capability. The enhanced version can also route variable-length packets without doing packet reassembly at the output.

Original language	English (US)
Pages (from-to)	577-589
Number of pages	13
Journal	Computer Communications
Volume	25
Issue number	6
DOIs	https://doi.org/10.1016/S0140-3664(01)00425-X
State	Published - Apr 1 2002

Keywords

Arbitration
Input buffered switch
Switch architecture
Terabit switching

ASJC Scopus subject areas

Computer Networks and Communications

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10.1016/S0140-3664(01)00425-X

Cite this

@article{bffb1b419582466d806264489291bd35,

title = "Design and analysis of enhanced Abacus switch",

abstract = "Combined input-output buffering with a moderate speedup for internal switch fabric has been considered as the most feasible solution to build large-capacity packet switches. This paper describes several schemes to further scale up our previously proposed Abacus switch [IEEE J. Select. Areas Commun. 15 (1997) 830] to multiple terabit per second. The Abacus switch implements the arbiter in a distributed manner, allowing the switch to be scaled in both the port speed and the switch capacity. The switch can be easily implemented using crosspoint switch chips with self-routing capability. The enhanced version can also route variable-length packets without doing packet reassembly at the output.",

keywords = "Arbitration, Input buffered switch, Switch architecture, Terabit switching",

author = "Park, {J. S.} and {Jonathan Chao}, H.",

year = "2002",

month = apr,

day = "1",

doi = "10.1016/S0140-3664(01)00425-X",

language = "English (US)",

volume = "25",

pages = "577--589",

journal = "Computer Communications",

issn = "0140-3664",

publisher = "Elsevier B.V.",

number = "6",

}

TY - JOUR

T1 - Design and analysis of enhanced Abacus switch

AU - Park, J. S.

AU - Jonathan Chao, H.

PY - 2002/4/1

Y1 - 2002/4/1

N2 - Combined input-output buffering with a moderate speedup for internal switch fabric has been considered as the most feasible solution to build large-capacity packet switches. This paper describes several schemes to further scale up our previously proposed Abacus switch [IEEE J. Select. Areas Commun. 15 (1997) 830] to multiple terabit per second. The Abacus switch implements the arbiter in a distributed manner, allowing the switch to be scaled in both the port speed and the switch capacity. The switch can be easily implemented using crosspoint switch chips with self-routing capability. The enhanced version can also route variable-length packets without doing packet reassembly at the output.

AB - Combined input-output buffering with a moderate speedup for internal switch fabric has been considered as the most feasible solution to build large-capacity packet switches. This paper describes several schemes to further scale up our previously proposed Abacus switch [IEEE J. Select. Areas Commun. 15 (1997) 830] to multiple terabit per second. The Abacus switch implements the arbiter in a distributed manner, allowing the switch to be scaled in both the port speed and the switch capacity. The switch can be easily implemented using crosspoint switch chips with self-routing capability. The enhanced version can also route variable-length packets without doing packet reassembly at the output.

KW - Arbitration

KW - Input buffered switch

KW - Switch architecture

KW - Terabit switching

UR - http://www.scopus.com/inward/record.url?scp=0036532780&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036532780&partnerID=8YFLogxK

U2 - 10.1016/S0140-3664(01)00425-X

DO - 10.1016/S0140-3664(01)00425-X

M3 - Article

AN - SCOPUS:0036532780

SN - 0140-3664

VL - 25

SP - 577

EP - 589

JO - Computer Communications

JF - Computer Communications

IS - 6

ER -

Design and analysis of enhanced Abacus switch

Abstract

Keywords

ASJC Scopus subject areas

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